Bubble sort slower with -O3 than -O2 with GCC

Looks like GCC's naivete about store-forwarding stalls is hurting its auto-vectorization strategy here. See also https://easyperf.net/blog/2018/03/09/Store-forwarding for some practical benchmarks on Intel with HW perf counters, and What are the costs of failed store-to-load forwarding on x86?

(gcc -O3 enables -ftree-vectorize and a few other options not included by -O2, e.g. if-conversion to branchless cmov, which is another way -O3 can hurt with data patterns GCC didn't expect. By comparison, clang enables auto-vectorization even at -O2, although some of its optimizations are still only on at -O3)

It's doing 64-bit loads (and branching to store or not) on pairs of ints. This means, if we swapped last iteration, this load comes half from that store, half from fresh memory, so we get a store-forwarding stall after every swap. (https://agner.org/optimize/). But Bubble Sort often has long chains of swapping every iteration as an element bubbles far, so this is really bad.

(Bubble Sort is bad in general, especially if implemented naively without keeping the previous iteration's 2nd element around in a register. It can be interesting to analyze the asm details of exactly why it sucks, so fair enough for wanting to try.)

Anyway, this is pretty clearly an anti-optimization you should report on https://gcc.gnu.org/bugzilla/ with the "missed-optimization" keyword. Scalar loads are cheap, and store-forwarding stalls are costly. (Can modern x86 implementations store-forward from more than one prior store? no, nor can uarches other than in-order Atom efficiently load when it partially overlaps with one previous store, and partially from data that has to come from L1d cache.)

Even better would be to keep buf[x+1] in a register and use it as buf[x] next iteration avoiding a store and load. (Like good hand-written asm bubblesort examples, a few of which exist on SO.)

If it wasn't for the store-forwarding stalls (which AFAIK GCC doesn't know about in its cost model), this strategy might be about break-even. SSE4.1 for a branchless pmind / pmaxd comparator might be interesting, but that would mean always storing and the C source doesn't do that.

If this strategy of double-width load had any merit, it would be better implemented with pure integer on a 64-bit machine like x86-64, where you can operate on just the low 32 bits with garbage (or valuable data) in the upper half. e.g.

## What GCC should have done,
## if it was going to use this 64-bit load strategy at all

        movsx   rax, edx         # apparently it wasn't able to optimize away your half-width signed loop counter into pointer math
        lea     rcx, [rdi+rax*4]   # Usually not worth an extra insn just to avoid an indexed load and indexed store, but let's keep it for easy comparison.
.L4:
        mov     rax, [rcx]       # into RAX instead of XMM0
        add     edx, 1
            #  pshufd  xmm2, xmm0, 0xe5
            #  movd    esi, xmm0
            #  movd    eax, xmm2
            #  pshufd  xmm1, xmm0, 225
        mov     rsi, rax
        rol     rax, 32   # swap halves, just like the pshufd
        cmp     esi, eax  # or eax, esi?  I didn't check which is which
        jle     .L2
        movq    QWORD PTR [rcx], rax   # conditionally store the swapped qword

(Or with BMI2 available from -march=native, rorx rsi, rax, 32 can copy-and-swap in one uop. Without BMIs, mov and swapping the original instead of the copy saves latency if running on a CPU without mov-elimination, such as Ice Lake with updated microcode.)

So total latency from load to compare is just integer load + 1 ALU operation (rotate). vs. XMM load -> movd. And its fewer ALU uops. This does nothing to help with the store-forwarding stall problem, though, which is still a showstopper. This is just an integer SWAR implementation of the same strategy, replacing 2x pshufd and 2x movd r32, xmm with just mov + rol.

Actually, there's no reason to use 2x pshufd here. Even if using XMM regs, GCC could have done one shuffle that swapped the low two elements, setting up for both the store and movd. So even with XMM regs, this was sub-optimal. But clearly two different parts of GCC emitted those two pshufd instructions; one even printed the shuffle constant in hex while the other used decimal! I assume one swapping and the other just trying to get vec[1], the high element of the qword.

slower than no flags at all

The default is -O0, consistent-debugging mode that spills all variables to memory after every C statement, so it's pretty horrible and creates big store-forwarding latency bottlenecks. (Somewhat like if every variable was volatile.) But it's successful store forwarding, not stalls, so "only" ~5 cycles, but still much worse than 0 for registers (a few modern uarches including Zen 2 have some special cases that are even better). The extra store and load instructions that have to go through the pipeline don't help.

It's generally not interesting to benchmark -O0. -O1 or -Og should be your go-to baseline for the compiler to do the basic amount of optimization a normal person would expect, without anything fancy, but also not intentionally gimp the asm by skipping register allocation.

Semi-related: optimizing Bubble Sort for size instead of speed can involve memory-destination rotate (creating store-forwarding stalls for back-to-back swaps), or a memory-destination xchg (implicit lock prefix -> very slow). See this code-golf answer.

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