Intel aims to regain chip manufacturing leadership by 2025

Under new management, Intel aims to recapture a crown that it owned for decades and regain technology leadership in manufacturing chips by 2025.

This will be challenging, as the company has to invest tens of billions of dollars and get its technology right in the wake of numerous missteps, but new CEO Pat Gelsinger said at an event that the big chipmaker is accelerating its investments in manufacturing processes and packaging innovations.

With the news, Intel offered one of the most detailed process and packaging technology roadmaps it has ever provided for its chip factories and showcased innovations that will power products through 2025 and beyond.

RibbonFET and PowerVia

Above: Intel 7 transistor

Image Credit: Intel

The company highlighted its planned swift adoption of next-generation extreme ultraviolet lithography (EUV), referred to as High Numerical Aperture (High NA) EUV.

Intel is positioned to receive the first High NA EUV production tool in the industry.

“Building on Intel’s unquestioned leadership in advanced packaging, we are accelerating our innovation roadmap to ensure we are on a clear path to process performance leadership by 2025,” Gelsinger said during the global Intel Accelerated webcast. “We are leveraging our unparalleled pipeline of innovation to deliver technology advances from the transistor up to the system level. Until the periodic table is exhausted, we will be relentless in our pursuit of Moore’s Law and our path to innovate with the magic of silicon.”

Santa Clara, California-based Intel definitely needs these innovations after a few years of setbacks.

“Intel had some very significant missteps. But I think there’s sort of this prevailing view that the manufacturing folks at Intel aren’t doing anything right now,” said David Kanter, an industry analyst and president of Real World Insight, in an interview with VentureBeat. “It’s not like they went on vacation for three or four years. They’re trying to go where the future of technology is, and they’re putting those things into production. There’s a broad consensus that the next evolution in transistor architecture is what we need to drive performance.”

The company also unveiled two “breakthrough” process technologies: RibbonFET, Intel’s first new transistor architecture in more than a decade, and PowerVia, an industry first for backside power delivery.

“The backside power delivery is more unique,” Kanter said. “It’s an example of a technology that is actually really complicated to get work. And the main benefit is in terms of performance. It helps those customers. But there’s a broad swath of customers, where it’s not about performance, it’s about cost.”

Intel also said it aims for continued leadership in advanced 3D packaging innovations with Foveros Omni and Foveros Direct technologies, which enable it to package chips in three dimensions.

Intel’s strategy has three legs. It is focusing on its factories for making internal products, like its microprocessors. It has Intel design groups that are design chips for external foundries. And it is investing heavily in factories that will make chips designed by outside companies.

New node naming

Above: Intel’s process technology innovations.

Image Credit: Intel

One of the big changes is in a category engineers often refer to as “marketecture.” Intel is changing the way it names its manufacturing processes so it is both more aligned with the rest of the industry and more accurate when it comes to talking about what kind of chips can be made at each stage of manufacturing.

“This is probably the most open disclosure of information that we’ve done in a very long time,” said Sanjay Natarajan, general manager of Intel’s logic development group and an executive who came back after Gelsinger became CEO this spring, in an interview with VentureBeat. “Pat talked before about how we do have an aspiration to be a leading provider of silicon globally.”

“We realized from a lot of people in the industry that our node naming is really not aligned with the rest of the industry,” he added. “Years ago, it used to represent a physical measurement on the transistor gate. It has long since stopped being a measurement of something specific there, and it’s more used as a label to describe technology. We’ve kind of realized that our naming has gotten confusing with the rest of the industry. Intel’s 10-nanometer was competitive with TSMC’s 7-nanometer and so on. Now we have a clear lexicon.”

Intel said it is also preparing for the “angstrom era” of semiconductors, as it will turn to a new way of describing its manufacturing nodes in a couple of generations.

“Intel has been more honest than TSMC and Samsung on node naming. I think Intel’s renaming is fair and credible in the context of what TSMC and Samsung are doing,” said Patrick Moorhead, an analyst at Moor Insights & Strategy, in an email to VentureBeat. “There is no industry standard way yet to compare these nodes.”

The industry has long recognized that traditional nanometer-based process node naming stopped matching the actual gate-length metric in 1997. Today, Intel introduced a new naming structure for its process nodes, creating a clear and consistent framework to give customers a more accurate view of process nodes across the industry, Natarajan said.

“I think Intel’s renaming is pretty consistent with the foundry naming scheme,” said Kanter. “For historical reference, things got out of sync because of TSMC’s 16nm process, which was really their 20nm process with FinFET transistors. So it didn’t really improve density (but the FinFETs boosted performance), but TSMC decided to call it 16nm anyway … and the whole industry followed. I think a lot of the motivation here is adopting terminology that allows effective communication and understanding throughout the community of customers, suppliers, press, analysts, investors, etc. And generally, I think the renaming will help folks understand the situation more accurately.”

Intel said the clarity is more important than ever with the launch of Intel Foundry Services, which will manufacture chips designed by other companies.

“The innovations unveiled today will not only enable Intel’s product roadmap; they will also be critical for our foundry customers,” Gelsinger said. “The interest in IFS has been strong. IFS is off to the races.”

Intel 7, Intel 4, and Intel 3

Above: Intel transistor cross-section.

Image Credit: Intel

Intel 7 appears to describe the equivalent of 7-nanometer manufacturing at rivals such as TSMC. Intel 7 delivers an approximately 10% to 15% performance-per-watt increase versus the previous generation, which was called Intel 10-nanometer SuperFin, based on FinFET transistor optimizations.

Intel 7 will be featured in products such as Alder Lake for clients in 2021 and Sapphire Rapids for the datacenter, with the latter expected to be in production in the first quarter of 2022.

Intel 4 fully embraces EUV lithography to print incredibly small features using ultra-short wavelength light. With an approximately 20% performance-per-watt increase, along with area improvements, Intel 4 will be ready for production in the second half of 2022 for products shipping in 2023, including Meteor Lake for client and Granite Rapids for the datacenter.

“What they’re probably trying to communicate is a little denser than five, certainly not as dense as the next one,” Kanter said. “I think it is reasonably accurate. One thing to keep in mind is that there’s a real divergence here in how area and power and performance are going to scale. And in that, I think Intel has set a bit more aggressive on performance than TSMC. And on density, it’s maybe a little less aggressive than TSMC.”

Intel 3 leverages further FinFET optimizations and increased EUV to deliver an 18% performance-per-watt increase over Intel 4, along with additional area improvements. Intel 3 will be ready to begin manufacturing products in the second half of 2023.

The angstrom era

Above: Intel CEO Pat Gelsinger

Image Credit: Intel

Intel 20A ushers in the angstrom era with two breakthrough technologies: RibbonFET and PowerVia. RibbonFET, Intel’s implementation of a gate-all-around transistor, will be the company’s first new transistor architecture since it pioneered FinFET in 2011.

The technology delivers faster transistor switching speeds while achieving the same drive current as multiple fins in a smaller footprint. PowerVia is Intel’s unique industry-first implementation of backside power delivery, optimizing signal transmission by eliminating the need for power routing on the front side of the wafer.

“Part of the reason we’re going to the term 20A is that we are bringing a few breakthrough innovations to light in this technology,” Natarajan said. “One is our RibbonFET, which is a new transistor architecture. The other is PowerVia, which is a breakthrough interconnect innovation.”

Intel 20A is expected to ramp in 2024.

“We have a clear path to process leadership,” Natarajan said. “In 2024, the Intel 20A node gets us to parity, and then Intel 18A gets us to leadership in 2025. Pat has put his foot on the gas for us, and this is an accelerated cadence of innovation.”

2025 and beyond

Above: Ann Kelleher, senior vice president and general manager of Technology Development.

Image Credit: Intel

Beyond Intel 20A, Intel 18A is already in development for early 2025, with refinements to RibbonFET that will deliver another major jump in transistor performance. The company is also working to define, build, and deploy next-generation High NA EUV and expects to receive the first production tool in the industry.

Intel is partnering closely with ASML to assure the success of this industry breakthrough beyond the current generation of EUV.

“Intel has a long history of foundational process innovations that have propelled the industry forward by leaps and bounds,” said Ann Kelleher, senior vice president and general manager of Technology Development, in the broadcast. “We led the transition to strained silicon at 90nm, to high-k metal gates at 45nm, and to FinFET at 22nm. Intel 20A will be another watershed moment in process technology with two groundbreaking innovations: RibbonFET and PowerVia.”

With Intel’s new IDM 2.0 strategy, the packaging is becoming even more important to realize the benefits of Moore’s Law.

Intel said embedded multi-die interconnect bridge (EMIB) continues to lead the industry as the first 2.5D embedded bridge solution, with products shipping since 2017. Sapphire Rapids will be the first Xeon datacenter product to ship in volume with EMIB. It will also be the first dual-reticle-sized device in the industry, delivering nearly the same performance as a monolithic design. Beyond Sapphire Rapids, the next generation of EMIB will move from a 55-micron bump pitch to 45 microns.

On top of that, Foveros will leverage wafer-level packaging capabilities to provide a first-of-its-kind 3D stacking solution. Meteor Lake will be the second-generation implementation of Foveros in a client product and features a bump pitch of 36 microns, tiles spanning multiple technology nodes, and a thermal design power range from 5 watts to 125 watts.

Foveros Omni ushers in the next generation of Foveros technology by promising flexibility with performance 3D stacking technology for die-to-die interconnect and modular designs. Foveros Omni allows die disaggregation, mixing multiple top die tiles with multiple base tiles across mixed fab nodes, and is expected to be ready for volume manufacturing in 2023.

Foveros Direct moves to direct copper-to-copper bonding for low-resistance interconnects and blurs the boundary between where the wafer ends and the package begins. Foveros Direct enables sub-10 micron bump pitches providing an order of magnitude increase in the interconnect density for 3D stacking, opening new concepts for functional die partitioning that were previously unachievable. Foveros Direct is complementary to Foveros Omni and is also expected to be ready in 2023.

The breakthroughs discussed today were primarily developed at Intel’s facilities in Oregon and Arizona, cementing the company’s role as the only leading-edge player with both research and development and manufacturing in the U.S., Intel said.

Additionally, the innovations draw on close collaboration with an ecosystem of partners in both the U.S. and Europe. Deep partnerships are key to bringing foundational innovations from the lab to high-volume manufacturing, and Intel is committed to partnering with governments to strengthen supply chains and drive economic and national security.

The company closed its webcast by confirming more details on its Intel InnovatiON event, which will be held in San Francisco and online October 27-28, 2021.