Arm’s William Wang considers how to increase the performance and programmability of persistent applications through using battery to protect the on-chip volatile cache hierarchy.

Cadence’s Paul McLellan finds that ransomware is getting more sophisticated, and more difficult to eradicate and defend against, with potentially life-threatening consequences.

Synopsys’ Jonathan Knudsen digs into 5G and how software security and networking intersect, particularly when using third-party code.

Siemens EDA’s Lee Harrison argues that one thing essential to enabling Level 5 autonomous driving is the ability to communicate securely with a vehicle over-the-air.

Ansys’ Tyler Ferris and Theresa Duncan examine how a trace reinforcement workflow can be used to model and test PCBs for specific stressors and use-environments to determine failure risks before physical prototyping.

In a blog for SEMI, Prof. Sang Won Yoon of the State University of New York at Binghamton examines how to implement a smart manufacturing solution in the PCB assembly for yield and throughput improvement.

A Brewer Science writer explains wafer-level packaging and how it can bring down cost while allowing higher levels of integration.

Memory blogger Ron Neale chats with Carlos Paz de Araujo of the University of Colorado in Colorado Springs and Symetrix about the challenges ferroelectric RAM has faced and the opportunities at the most advanced process lithographies.

Semico Research’s Rich Wawrzyniak looks at how the current expansion of the AI market mirrors that of the PC and checks out the BrainChip architecture.

Applied Materials’ Sony Varghese finds that today’s DRAM makers are running up against the same dielectric scaling challenges faced by leading-edge logic makers around 20 years ago.

Agnisys’ Anupam Bakshi dives into the UVM Register Abstraction Layer and how to make sure that these registers work correctly.