Excess-3

Stibitz code Digits Tracks Digit values 8  4 - 2 - 1 Weight(s) Continuity Cyclic Minimum distance Maximum distance 4 Redundancy 0.7 Lexicography Complement

• v
• t
• e

Excess-3 , 3-excess or 10-excess-3 binary code (often abbreviated as XS-3 , 3XS or X3 ), shifted binary or Stibitz code (afterGeorge Stibitz,who built a relay-based adding machine in 1937) is a self-complementarybinary-coded decimal (BCD) code andnumeral system. It is a biased representation . Excess-3 code was used on some older computers as well as in cash registers and hand-held portable electronic calculators of the 1970s, among other uses.

Representation [ edit ]

Biased codes are a way to represent values with a balanced number of positive and negative numbers using a pre-specified number N as a biasing value. Biased codes (andGray codes) are non-weighted codes. In excess-3 code, numbers are represented as decimal digits, and each digit is represented by fourbits as the digit value plus 3 (the "excess" amount):

• The smallest binary number represents the smallest value ( 0 − excess ).
• The greatest binary number represents the largest value ( 2 N +1 − excess − 1 ).

Excess-3 / Stibitz code Decimal Excess-3 Stibitz BCD 8-4-2-1 Binary 4-of-8Hamming extension −3 0000 pseudo-tetrade N/A N/A N/A N/A −2 0001 pseudo-tetrade N/A N/A N/A N/A −1 0010 pseudo-tetrade N/A N/A N/A N/A 0 0011 0011 0000 0000 … 10 … 0011 1 0100 0100 0001 0001 … 11 … 1011 2 0101 0101 0010 0010 … 10 … 0101 3 0110 0110 0011 0011 … 10 … 0110 4 0111 0111 0100 0100 … 00 … 1000 5 1000 1000 0101 0101 … 11 … 0111 6 1001 1001 0110 0110 … 10 … 1001 7 1010 1010 0111 0111 … 10 … 1010 8 1011 1011 1000 1000 … 00 … 0100 9 1100 1100 1001 1001 … 10 … 1100 10 1101 pseudo-tetrade pseudo-tetrade 1010 N/A N/A 11 1110 pseudo-tetrade pseudo-tetrade 1011 N/A N/A 12 1111 pseudo-tetrade pseudo-tetrade 1100 N/A N/A 13 N/A N/A pseudo-tetrade 1101 N/A N/A 14 N/A N/A pseudo-tetrade 1110 N/A N/A 15 N/A N/A pseudo-tetrade 1111 N/A N/A

To encode a number such as 127, one simply encodes each of the decimal digits as above, giving (0100, 0101, 1010).

Excess-3 arithmetic uses differentalgorithms than normal non-biased BCD or binarypositional system numbers. After adding two excess-3 digits, the raw sum is excess-6. For instance, after adding 1 (0100 in excess-3) and 2 (0101 in excess-3), the sum looks like 6 (1001 in excess-3) instead of 3 (0110 in excess-3). In order to correct this problem, after adding two digits, it is necessary to remove the extra bias by subtracting binary 0011 (decimal 3 in unbiased binary) if the resulting digit is less than decimal 10, or subtracting binary 1101 (decimal 13 in unbiased binary) if anoverflow (carry) has occurred. (In 4-bit binary, subtracting binary 1101 is equivalent to adding 0011 and vice versa.)

Motivation [ edit ]

The primary advantage of excess-3 coding over non-biased coding is that a decimal number can benines' complemented (for subtraction) as easily as a binary number can beones' complemented: just by inverting all bits.Also, when the sum of two excess-3 digits is greater than 9, the carry bit of a 4-bit adder will be set high. This works because, after adding two digits, an "excess" value of 6 results in the sum. Because a 4-bit integer can only hold values 0 to 15, an excess of 6 means that any sum over 9 will overflow (produce a carry out).

Another advantage is that the codes 0000 and 1111 are not used for any digit. A fault in a memory or basic transmission line may result in these codes. It is also more difficult to write the zero pattern to magnetic media.

Example [ edit ]

BCD 8-4-2-1 to excess-3 converter example inVHDL:

entity bcd8421xs3 is
  port (
    a   : in    std_logic;
    b   : in    std_logic;
    c   : in    std_logic;
    d   : in    std_logic;

    an  : buffer std_logic;
    bn  : buffer std_logic;
    cn  : buffer std_logic;
    dn  : buffer std_logic;

    w   : out   std_logic;
    x   : out   std_logic;
    y   : out   std_logic;
    z   : out   std_logic
  );
end entity bcd8421xs3;

architecture dataflow of bcd8421xs3 is
begin
    an  <=  not a;
    bn  <=  not b;
    cn  <=  not c;
    dn  <=  not d;

    w   <=  (an and b  and d ) or (a  and bn and cn)
         or (an and b  and c  and dn);
    x   <=  (an and bn and d ) or (an and bn and c  and dn)
         or (an and b  and cn and dn) or (a  and bn and cn and d);
    y   <=  (an and cn and dn) or (an and c  and d )
         or (a  and bn and cn and dn);
    z   <=  (an and dn) or (a  and bn and cn and dn);

end architecture dataflow; -- of bcd8421xs3

Extensions [ edit ]