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Open-source, configurable HDMI output for FPGAs

 4 years ago
source link: https://github.com/hdl-util/hdmi
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hdmi

SystemVerilog code for HDMI 1.4a video/audio output on an FPGA .

Why?

Most free and open source HDMI source (computer/gaming console) implementations actually output a DVI signal, which HDMI sinks (TVs/monitors) are backwards compatible with. To support audio and other HDMI-only functionality, a true HDMI signal must be sent. The code in this repository lets you do that without having to license an HDMI IP block from anyone.

Demo: VGA-compatible text mode, 720x480p on a Dell Ultrasharp 1080p Monitor

YjUNBj6.gif

Usage

  1. Take files from src/ and add them to your own project. If you use hdlmake , you can add this repository itself as a remote module. Note that hdlmake may not resolve altera_gpio_lite properly, since it does not define ALTERA_RESERVED_QIS during Quartus project resolution.
  2. Other helpful modules for displaying text / generating sound are also available in this GitHub organization.
  3. Consult the simple usage example in top/top.sv .
  4. See hdmi-demo for code that runs the demo as seen the demo GIF.
  5. Read through the parameters in hdmi.sv and tailor any instantiations to your situation.
  6. Please create an issue if you run into a problem or have any questions. Make sure you have consulted the troubleshooting section first.

Platform Support

  • Altera
  • Xilinx (untested but should work)
  • Lattice (unknown)

To-do List (upon request)

  • 24-bit color
  • Data island packets
    • Null packet
    • ECC with BCH systematic encoding GF(2^8)
    • Audio clock regeneration
    • L-PCM audio
      • 2-channel
      • 3-channel to 8-channel
    • 1-bit audio
    • Audio InfoFrame
    • Auxiliary Video Information InfoFrame
    • Source Product Descriptor InfoFrame
    • MPEG Source InfoFrame
      • NOTE—Problems with the MPEG Source Infoframe have been identified that were not able to be fixed in time for CEA-861-D. Implementation is strongly discouraged until a future revision fixes the problems
    • Gamut Metadata
  • Video formats 1, 2, 3, 4, 16, 17, 18, and 19
  • VGA-compatible text mode
    • IBM 8x16 font
    • Alternate fonts
  • Other color formats (YCbCr, deep color, etc.)
  • Support other video id codes
    • Interlaced video
    • Pixel repetition
  • Special I/O features
    • Double Data Rate I/O (DDRIO)

Pixel Clock

You'll need to set up a PLL for producing the two HDMI clocks. The pixel clock for each supported format is shown below:

Video Resolution Video ID Code(s) Refresh Rate Pixel Clock Frequency 640x480 1 60Hz 25.2MHz 640x480 1 59.94Hz 25.175MHz 720x480 2, 3 60Hz 27.027MHz 720x480 2, 3 59.94Hz 27MHz 1280x720 4 60Hz 74.25MHz 1280x720 4 59.94Hz 74.176MHz 1920x1080 16 60Hz 148.5MHz 1920x1080 16 59.94Hz 148.352MHz 720x576 17, 18 50Hz 27MHz 1280x720 19 50Hz 74.25MHz

The second clock is a clock 10 times as fast as the pixel clock. Even if your FPGA only has a single PLL, the Altera MegaWizard (or the Xilinx equivalent) should still be able to produce both. You can avoid using two different multiplication factors, with the DDRIO feature, which only requires the second clock to be 5 times as fast.

L-PCM Audio Bitrate / Sampling Frequency

Both audio bitrate and frequency are specified as parameters of the HDMI module. Bitrate can be any value from 16 through 24. Below is a simple mapping of sample frequency to the appropriate parameter

Sampling Frequency AUDIO_RATE value 32 kHz 32000 44.1 kHz 44100 88.2 kHz 88200 176.4 kHz 176400 48 kHz 48000 96 kHz 96000 192 kHz 192000

Things to be aware of / Troubleshooting

  • Limited resolution: some FPGAs don't support I/O at speeds high enough to achieve 720p/1080p
    • Workaround: use DDR/other special I/O features like I/O serializers
    • Workaround: Altera FPGA users can try to specify speed grade C6 and see if it works, though yours may be C7 or C8. If it doesn't work, try enabling DDRIO.
  • FPGA does not support TMDS: many FPGAs without a dedicated HDMI output don't support TMDS
    • You should be able to directly use LVDS (3.3v) instead, tested up to 720x480
    • This might not work if your video has a high number of transitions or you plan to use higher resolutions
    • Solution: AC-couple the 3.3v LVDS wires to by adding 100nF capacitors in series, as close to the transmitter as possible
  • Poor wiring: if you're using a breakout board or long lengths of untwisted wire, there might be a few pixels that jitter due to interference
    • Make sure you have all the necessary pins connected (GND pins, etc.)
    • Try switching your HDMI cable; some cheap cables like these I got from Amazon have poor shielding
  • Hot-Plug unaware: all modules are unaware of hotplug
    • This shouldn't affect anything in the long term; the only stateful value is hdmi.tmds_channel.acc
    • You should decide hotplug behavior (i.e. pause/resume on disconnect/connect, or ignore it)
  • EDID not implemented: it is assumed you know what format you want at synthesis time, so there is no dynamic decision on video format
    • To be implemented in a display protocol independent manner
  • SCL/SCA voltage level: though unused by this implementation...it is I2C on a 5V logic level, as confirmed in the TPD12S016 datasheet , which is unsupported by most FPGAs
    • Solution: use a bidirectional logic level shifter compatible with I2C to convert 3.3v LVTTL to 5v
    • Solution: use 2.5V I/O standard with 6.65k pull-up resistors to 3.3v (as done in J13 on the Arduino MKR Vivado 4000 schematic )
      • To investigate: why do they do this, and does it work at all?

Licensing

Dual-licensed under Apache License 2.0 and MIT License.

Alternatives

If you know of another good alternative, open and issue and it will be added.

Reference Documents

These documents are not hosted here! They are available on Library Genesis and at other locations.

Special Thanks


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