UPDuino: a $9.99 FPGA
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A few years ago, when our kids were young, we started a ridiculous family tradition of "Summer Christmas". One of the rules of this invented holiday is that we all get to self-gift something we'd like. This year I gave myself a cheap FPGA board that I'd seen over on hackaday. In part because it is cheap, but also because I'm always dabbling with FPGAs, and am now starting to think about a protocol analyzer.
The FPGA is a Lattice UltraPlus 5K, which has some interesting attributes:
- 128 Kbytes of internal RAM, in addition to 15 Kbytes of block RAM
- 2 IP cores for I2C and SPI
- supported by project icestorm
What makes it a good fit for a protocol analyzer is the relatively large RAM. Being able to capture thousands of events makes it much more useful. With an FT813 driving a large touch screen the whole thing could be pretty sweet:
So how much FPGA do you get for $9.99 shipped? Mine came folded in an anti-static bag, stuffed in a regular envelope. It arrived intact, though others have not been so lucky:
Inside was the UPDuino v1.0 
This thread (where people are criticizing the board layout) has a revealing comment from the maker gjennings himself:
On board quality - I paid a High School/College kid in Sri Lanka to do the board; I will give him your feedback. If you'd like, I can give you the UPDuino V2.0 schematic and layout to review. Just let me know
I sell these boards at cost and have developed a decent time commitment in testing and shipping them. So, if they are not useful let me know.
There's very little documentation for the board. In particular there is no "getting started" guide. But you do get the complete Eagle design files:
Using these I was able to get it running a LED-blink bitstream in a few minutes.
The low-end Lattice FPGAs are very simple to configure. All you have to do is write the bitstream (a 104 Kbyte configuration blob) directly into the onboard SPI flash and then reset the FPGA. A perfect job for a SPIDriver ! Hookup uses the regular SPI signals plus the extra "A" signal is connected to CRESET_B to reset the FPGA:
The short loader is in iceprog.py , for Python 2 or 3. It takes 4.6 seconds to load a bitstream into flash. The result is a blinking LED - success!
The next step is to get a J1 running on the FPGA, and maybe get it talking to a Gameduino 3 , then to capture signals into its huge 128 Kbyte RAM.
Some resources:
This is a short, clear explanation of the UltraPlus configuration process.
This project was helpful, because it includes a couple of pre-built LED flasher bitstreams.
A thread about the UPDuino.
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