Chips-2.0: FPGA Design Suite Based on C to Verilog Design Flow
source link: https://www.tuicool.com/articles/hit/emERrii
Go to the source link to view the article. You can view the picture content, updated content and better typesetting reading experience. If the link is broken, please click the button below to view the snapshot at that time.
Chips - 2.0
Chips is a high level, FPGA design tool inspired by Python .
Try it out
Why not try the Chips web app.
Design components in C, design FPGAs in Python
In Chips, a design resembles a network of computers implemented in a single chip. A chip consists of many interconnected components operating in parallel. Each component acts like a computer running a C program.
Components communicate with each other sending messages across buses. The design of a chip - the components and the connections between them - is carried in Python.
Chips come in three parts:
- A Python library to build and simulate chips by connecting together digital components using high speed buses.
- A collection of ready made digital components.
- A C-to-hardware compiler to make new digital components in the C programming language.
A quick example
from chips.api.api import * #create a new chip chip = Chip("knight_rider") #define a component in C scanner = Component(C_file = """ /* Knight Rider */ int leds = output("leds"); void main(){ unsigned shifter = 1; while(1){ while(shifter != 0x80){ fputc(shifter, leds); shifter <<= 1; wait_clocks(5000000); } while(shifter != 0x01){ fputc(shifter, leds); shifter >>= 1; wait_clocks(5000000); } } } """, inline=True) #capture simulation output in Python scanner_output = Response(chip, "scanner", "int") #add scanner to chip and connect scanner(chip, inputs = {}, outputs = {"leds":scanner_output}) #generate synthesisable verilog code chip.generate_verilog() #run simulation in Python chip.simulation_reset() while len(scanner_output) < 16: chip.simulation_step() #check the results print list(scanner_output)
Work at a higher level of abstraction
In Chips, the details of gates, clocks, resets, finite-state machines and flow-control are handled by the tool, this leaves the designer free to think about the architecture and the algorithms. This has some benefits:
- Designs are simpler.
- Simpler designs take much less time to get working.
- Simpler designs are much less likely to have bugs.
With Chips the batteries are included
With traditional Hardware Description Languages, there are many restrictions on what can be translated into hardware and implemented in a chip.
With Chips almost all legal code can be translated into hardware. This includes division, single and double precision IEEE floating point, maths functions, trig-functions, timed waits, pseudo-random numbers and recursive function calls.
Python is a rich verification environment
Chips provides the ability to simulate designs natively in Python. Python is an excellent programming language with extensive libraries covering many application domains. This makes it the perfect environment to verify a chip.
NumPy , SciPy and MatPlotLib will be of interest to engineers, but that's just the start .
Under the hood
Behind the scenes, Chips uses some novel techniques to generate compact and efficient logic - a hybrid of software and hardware.
Not only does the compiler translate the C code into CPU instructions, it also generates a customised pipelined RISC CPU on the fly. The CPU provides the optimal instruction set for any particular C program.
By minimising the logic required to perform each concurrent task, designers can reduce power and area or cost. Performance gains can be achieved by increasing the number of concurrent tasks in a single device (tens in a small device to around a thousand or more large device).
While the code generated by chips is compact and efficient, die hard FPGA designers will be pleased to know that they can still hand craft performance critical data paths if they need to. There are even a few hand crafted components thrown in!
Install from github
$ git clone --recursive https://github.com/dawsonjon/Chips-2.0.git $ cd Chips-2.0 $ sudo python setup install
Install from PyPi
$ pip-install chips
Recommend
-
55
Verilog 6502 Back to projects Here, with full source co...
-
34
Big news! You can use the 8bitworkshop IDE towrite Verilog code, and see it executed instantly in real-time on a simulated CRT. Most computers are fast enough to render a game at 60 Hz, which requires simulating Verilog...
-
40
SweRV RISC-V core from Western Digital This repository contains the SweRV core design RTL License By contributing to this project, you agree that your contribution is governed by
-
5
FPGA-based Oracle RDBMS passwords solver6-Dec-2009: FPGA-based Oracle RDBMS passwords solver I wrote small article about FPGA-based Oracle RDBMS passwords solver: http://conus.info/ops/ops.ht...
-
0
Transform 2021 Join us for the world’s leading event about accelerating enterprise transformation with AI and Data, for enterprise technology decision-makers, presented by the #1 publisher in AI...
-
6
Verilog to Routing (VTR) Introduction The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR de...
-
2
News Intel’s FPGA Day Unveils 3 Collabs to Create More FPGA-based IPU Designs one day ago by Jake Hertz Seeing these advantages...
-
3
学fpga(在线verilog编程)
-
2
学fpga(从verilog到hls)
-
5
STEPFPGA supports Verilog on c...
About Joyk
Aggregate valuable and interesting links.
Joyk means Joy of geeK