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P-bits: Bridging the gap between standard bits and q-bits

 4 years ago
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Abstract

We introduce the concept of a probabilistic or p-bit, intermediate between the standard bits of digital electronics and the emerging q-bits of quantum computing. We show that low barrier magnets or LBMs provide a natural physical representation for p-bits and can be built either from perpendicular magnets designed to be close to the in-plane transition or from circular in-plane magnets. Magnetic tunnel junctions (MTJs) built using LBMs as free layers can be combined with standard NMOS transistors to provide three-terminal building blocks for large scale probabilistic circuits that can be designed to perform useful functions. Interestingly, this three-terminal unit looks just like the 1T/MTJ device used in embedded magnetic random access memory technology, with only one difference: the use of an LBM for the MTJ free layer. We hope that the concept of p-bits and p-circuits will help open up new application spaces for this emerging technology. However, a p-bit need not involve an MTJ; any fluctuating resistor could be combined with a transistor to implement it, while completely digital implementations using conventional CMOS technology are also possible. The p-bit also provides a conceptual bridge between two active but disjoint fields of research, namely, stochastic machine learning and quantum computing. First, there are the applications that are based on the similarity of a p-bit to the binary stochastic neuron (BSN), a well-known concept in machine learning. Three-terminal p-bits could provide an efficient hardware accelerator for the BSN. Second, there are the applications that are based on the p-bit being like a poor man's q-bit. Initial demonstrations based on full SPICE simulations show that several optimization problems, including quantum annealing are amenable to p-bit implementations which can be scaled up at room temperature using existing technology.

I. INTRODUCTION

A. Between a bit and a q-bit

Modern digital circuits are based on binary bits that can take on one of the two values, 0 and 1, and are stored using well-developed technologies at room temperature. At the other extreme are quantum circuits based on q-bits which are delicate superpositions of 0 and 1, requiring the development of novel technologies typically working at cryogenic temperatures. This article is about what we call probabilistic bits or p-bits that are classical entities fluctuating rapidly between 0 and 1. We will argue that we can use existing technology to build what we call p-circuits that should function robustly at room temperature while addressing some of the applications commonly associated with quantum circuits ().

FIG. 1. Between a bit and a q-bit: the p-bit Digital computers use deterministic strings of 0's and 1's called bits to represent information in a binary code. The emerging field of quantum computing is based on q-bits representing a delicate superposition of 0 and 1 that typically requires cryogenic temperatures. We envision a class of probabilistic computers or p-computers operating robustly at room temperature with existing technology based on p-bits which are classical entities fluctuating rapidly between 0 and 1. Although spins provide a nice unifying paradigm for illustrating the transition from bits to p-bits and q-bits, it should be noted that the physical realization of a p-bit need not involve spins or spintronics; non-spintronic implementations can be just as feasible.

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How would we represent a p-bit physically? Let us first consider the two extremes, namely, the bit and the q-bit. A q-bit is often represented by the spin of an electron, while a bit is often represented by binary voltage levels in digital elements like flip-flops and floating-gate transistors. However, bits can also be represented by magnets 1. E. Chen, D. Apalkov, Z. Diao, A. Driskill-Smith, D. Druist, D. Lottis, V. Nikitin, X. Tang, S. Watts, S. Wang, S. Wolf, A. W. Ghosh, J. Lu, S. J. Poon, M. Stan, W. Butler, S. Gupta, C. K. A. Mewes, T. Mewes, and P. Visscher, “ Advances and future prospects of spin-transfer torque random access memory ,” IEEE Trans. Magn. 46 , 1873– 1878 (2010). https://doi.org/10.1109/TMAG.2010.2042041 which are basically collections of a very large number of spins. In a magnet, internal interactions make the energy a minimum when the spins all point either parallel or anti-parallel to a specific direction, called the easy axis. These two directions represent 0 and 1 and are separated by an energy barrier, E b , which ensures their stability.

How large is the barrier? A nanomagnet flips back and forth between 0 and 1 at a rate determined by the energy barrier: τ∼τ0  exp (Eb/kBT) , where τ 0 typically has a value between picoseconds and nanoseconds. 2. L. Lopez-Diaz, L. Torres, and E. Moro, “ Transition from ferromagnetism to superparamagnetism on the nanosecond time scale ,” Phys. Rev. B 65 , 224406 (2002). https://doi.org/10.1103/PhysRevB.65.224406 Assuming a τ 0 of a nanosecond, a barrier of E b  ∼ 40 k B T , for example, would retain a 0 (or a 1) for ∼10 years, making it suitable for long term memory, while a smaller barrier of E b  ∼ 14 k B T would only ensure a short term memory ∼1 ms. 3. N. Locatelli, A. Mizrahi, A. Accioly, R. Matsumoto, A. Fukushima, H. Kubota, S. Yuasa, V. Cros, L. G. Pereira, D. Querlioz et al. , “ Noise-enhanced synchronization of stochastic magnetic oscillators ,” Phys. Rev. Appl. 2 , 034009 (2014). https://doi.org/10.1103/PhysRevApplied.2.034009

It has been recognized that this stability problem also represents an opportunity. Unstable low barrier magnets (LBMs) could be used to implement useful functions like random number generation (RNG) 4. B. Parks, M. Bapna, J. Igbokwe, H. Almasi, W. Wang, and S. A. Majetich, “ Superparamagnetic perpendicular magnetic tunnel junctions for true random number generators ,” AIP Adv. 8 , 055903 (2018). https://doi.org/10.1063/1.5006422 5. D. Vodenicarevic, N. Locatelli, A. Mizrahi, J. Friedman, A. Vincent, M. Romera, A. Fukushima, K. Yakushiji, H. Kubota, S. Yuasa, S. Tiwari, J. Grollier, and D. Querlioz, “ Low-energy truly random number generation with superparamagnetic tunnel junctions for unconventional computing ,” Phys. Rev. Appl. 8 , 054045 (2017). https://doi.org/10.1103/PhysRevApplied.8.054045 6. D. Vodenicarevic, N. Locatelli, A. Mizrahi, T. Hirtzlin, J. S. Friedman, J. Grollier, and D. Querlioz, “ Circuit-level evaluation of the generation of truly random bits with superparamagnetic tunnel junctions ,” in Proceedings of 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (2018), pp. 1– 4 . by sensing the randomly fluctuating magnetization to provide a random time varying voltage. With such applications in mind, we would want magnets to have as low a barrier as possible so that many random numbers are generated in a given amount of time. Indeed a “zero” barrier magnet with E b ≤ k B T flipping back and forth in less than a nanosecond would be ideal.

How can we reduce the energy barrier? Since E b = H K M s Ω/2, the basic approach is to reduce the total magnetic moment by reducing volume Ω and/or engineer a small anisotropy field H K . 7. P. Debashis, R. Faria, K. Y. Camsari, and Z. Chen, “ Designing stochastic nanomagnets for probabilistic spin logic ,” IEEE Magn. Lett. 9 , 4305205 (2018). https://doi.org/10.1109/LMAG.2018.2860547 This can be done with perpendicular magnets (PMA) designed to be close to the in-plane transition. A less challenging approach seems to be to use circular in-plane magnets (IMA). 7. P. Debashis, R. Faria, K. Y. Camsari, and Z. Chen, “ Designing stochastic nanomagnets for probabilistic spin logic ,” IEEE Magn. Lett. 9 , 4305205 (2018). https://doi.org/10.1109/LMAG.2018.2860547 8. R. P. Cowburn, D. K. Koltsov, A. O. Adeyeye, M. E. Welland, and D. M. Tricker, “ Single-domain circular nanomagnets ,” Phys. Rev. Lett. 83 , 1042 (1999). https://doi.org/10.1103/PhysRevLett.83.1042 9. P. Debashis, R. Faria, K. Y. Camsari, J. Appenzeller, S. Datta, and Z. Chen, “ Experimental demonstration of nanomagnet networks as hardware for Ising computing ,” in Proceedings of 2016 IEEE International Electron Devices Meeting (IEDM) (2016), pp. 34.3.1– 34.3.4 . We will refer to all these possibilities collectively as LBMs as opposed to say, superparamagnets which have more specific connotations in different contexts. 3. N. Locatelli, A. Mizrahi, A. Accioly, R. Matsumoto, A. Fukushima, H. Kubota, S. Yuasa, V. Cros, L. G. Pereira, D. Querlioz et al. , “ Noise-enhanced synchronization of stochastic magnetic oscillators ,” Phys. Rev. Appl. 2 , 034009 (2014). https://doi.org/10.1103/PhysRevApplied.2.034009 10. B. Sutton, K. Y. Camsari, B. Behin-Aein, and S. Datta, “ Intrinsic optimization using stochastic nanomagnets ,” Sci. Rep. 7 , 44370 (2017). https://doi.org/10.1038/srep44370 11. R. Faria, K. Y. Camsari, and S. Datta, “ Low-barrier nanomagnets as p-bits for spin logic ,” IEEE Magn. Lett. 8 , 1– 5 (2017). https://doi.org/10.1109/LMAG.2017.2685358 12. K. Y. Camsari, R. Faria, B. M. Sutton, and S. Datta, “ Stochastic p-bits for invertible logic ,” Phys. Rev. X 7 , 031014 (2017). https://doi.org/10.1103/PhysRevX.7.031014 13. K. Y. Camsari, S. Salahuddin, and S. Datta, “ Implementing p-bits with embedded MTJ ,” IEEE Electron Device Lett. 38 , 1767– 1770 (2017). https://doi.org/10.1109/LED.2017.2768321 14. A. Mizrahi, T. Hirtzlin, A. Fukushima, H. Kubota, S. Yuasa, J. Grollier, and D. Querlioz, “ Neural-like computing with populations of superparamagnetic basis functions ,” Nat. Commun. 9 , 1533 (2018). https://doi.org/10.1038/s41467-018-03963-w 15. M. Bapna and S. A. Majetich, “ Current control of time-averaged magnetization in superparamagnetic tunnel junctions ,” Appl. Phys. Lett. 111 , 243107 (2017). https://doi.org/10.1063/1.5012091

We could use LBMs to represent the probabilistic bits or p-bits that we alluded to. We have argued that if these p-bits can be incorporated into proper transistor-like structures with gain, then the resulting three-terminal p-bits could be interconnected to build p-circuits that perform useful functions, 10. B. Sutton, K. Y. Camsari, B. Behin-Aein, and S. Datta, “ Intrinsic optimization using stochastic nanomagnets ,” Sci. Rep. 7 , 44370 (2017). https://doi.org/10.1038/srep44370 12. K. Y. Camsari, R. Faria, B. M. Sutton, and S. Datta, “ Stochastic p-bits for invertible logic ,” Phys. Rev. X 7 , 031014 (2017). https://doi.org/10.1103/PhysRevX.7.031014 16. B. Behin-Aein, V. Diep, and S. Datta, “ A building block for hardware belief networks ,” Sci. Rep. 6 , 29893 (2016). https://doi.org/10.1038/srep29893 not unlike the way transistors are interconnected to build useful digital circuits. However, unlike digital circuits, these probabilistic p-circuits incorporate features reminiscent of quantum circuits.

This connection was nicely articulated by Feynman in a seminal paper, 17. R. P. Feynman, “ Simulating physics with computers ,” Int. J. Theor. Phys. 21 , 467– 488 (1982). https://doi.org/10.1007/BF02650179 where he described a quantum computer that could provide an efficient simulation of quantum many-body problems. But to set the stage for quantum computers, he first described a probabilistic p-computer which could efficiently simulate classical many-body problems:

…“the other way to simulate a probabilistic nature, which I'll call N …is by a computer C which itself is probabilistic, …in which the output is not a unique function of the input …it simulates nature in this sense: that C goes from some …initial state …to some final state with the same probability that N goes from the corresponding initial state to the corresponding final state …If you repeat the same experiment in the computer a large number of times …it will give the frequency of a given final state proportional to the number of times, with approximately the same rate …as it happens in nature.”

There are many practical problems of great interest which involve large networks of probabilistic quantities. These problems should be simulated efficiently by p-computers of the type envisioned by Feynman. Our purpose here is to discuss appropriate hardware building blocks that can be used to build them 16. B. Behin-Aein, V. Diep, and S. Datta, “ A building block for hardware belief networks ,” Sci. Rep. 6 , 29893 (2016). https://doi.org/10.1038/srep29893 and possible applications they could be used for. In this context, let us note that although spins provide a nice unifying paradigm for illustrating the transition from bits to p-bits and q-bits, the physical realization of a p-bit need not involve spins or spintronics; non-spintronic implementations can be just as feasible.

B. Binary stochastic neuron (BSN)

Interestingly, the concept of a p-bit connects naturally to another concept well-known in the field of machine learning, namely, that of a binary stochastic neuron (BSN) 18. D. H. Ackley, G. E. Hinton, and T. J. Sejnowski, “ A learning algorithm for Boltzmann machines ,” Cognit. Sci. 9 , 147– 169 (1985). https://doi.org/10.1207/s15516709cog0901_7 19. R. M. Neal, “ Connectionist learning of belief networks ,” Artif. Intell. 56 , 71– 113 (1992). https://doi.org/10.1016/0004-3702(92)90065-6 whose response m i to an input I i can be described mathematically by mi=sgn[tanh Ii−r], (1) where r is a random number uniformly distributed between −1 and +1. 20. Equationcan be equivalently written as m i = sgn[tanh I i + r ]. Here, we are using bipolar variables m i = ±1 to represent the 0 and 1 states. If we use binary variables m i = 0, 1, the corresponding equation would look different. 21. The signum function (sgn) would be replaced by the step function (Θ) and the tanh function would be replaced by the sigmoid function ( σ ) such that mi=Θ[σ(2Ii)−r0] , where the random number r 0 is uniformly distributed between 0 and 1. When combined with a synaptic function described by Ii=∑jWij mj, (2) we have a probabilistic network that can be designed to perform a wide variety of functions through a proper choice of the weights, W ij . A separate bias term h i is often included in Eq., but we will not write it explicitly, assuming that it is included as the weighted input from an extra p-bit that is always +1.

Equationsandare widely used in many modern algorithms, but they are commonly implemented in software. Much work has gone into developing suitable hardware accelerators for matrix multiplication of the type described by Eq.(see, for example, Ref. 22. M. Hu, J. P. Strachan, Z. Li, E. M. Grafals, N. Davila, C. Graves, S. Lam, N. Ge, J. J. Yang, and R. S. Williams, “ Dot-product engine for neuromorphic computing: Programming 1t1m crossbar to accelerate matrix-vector multiplication ,” in Proceedings of the 53rd Annual Design Automation Conference ( ACM , 2016), p. 19. ). Three-terminal p-bits would provide a hardware accelerator for Eq.. Together, they would function like a probabilistic computer.

Note that a hardware accelerator for Eq.requires more than just an RNG. We need a tunable RNG whose output m i can be biased through the input terminal I i as shown in. Two distinct designs for a three-terminal p-bit have been described 12. K. Y. Camsari, R. Faria, B. M. Sutton, and S. Datta, “ Stochastic p-bits for invertible logic ,” Phys. Rev. X 7 , 031014 (2017). https://doi.org/10.1103/PhysRevX.7.031014 13. K. Y. Camsari, S. Salahuddin, and S. Datta, “ Implementing p-bits with embedded MTJ ,” IEEE Electron Device Lett. 38 , 1767– 1770 (2017). https://doi.org/10.1109/LED.2017.2768321 both of which use a magnetic tunnel junction (MTJ), a popular “spintronic” device used in magnetic random access memory (MRAM). 23. S. Bhatti, R. Sbiaa, A. Hirohata, H. Ohno, S. Fukami, and S. Piramanayagam, “ Spintronics based random access memory: A review ,” Mater. Today 20 , 530– 548 (2017). https://doi.org/10.1016/j.mattod.2017.07.007 However, MRAM applications use stable MTJs that can store information for many years, while a p-bit makes use of “bad” MTJs with low barriers.

FIG. 2. Three terminal p-bit: (a) a hardware implementation of the BSN [Eq.] requires a central stochastic element with input and output terminals that provide the ability to read and bias the element. (b) The stochastic element can be visualized as going back and forth between two low energy states at a rate that depends exponentially on the barrier E b that separates them: τ=τ0 exp (Δ/kBT) . (c) The bias terminal adjusts the relative energies of the two states, thereby controlling the probabilities of finding the element in the two states.

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The LBM-based implementation of the BSN described here is conceptually very different from a clocked approach using stable magnets where a stochastic output is obtained every time a clock pulse is applied. 16. B. Behin-Aein, V. Diep, and S. Datta, “ A building block for hardware belief networks ,” Sci. Rep. 6 , 29893 (2016). https://doi.org/10.1038/srep29893 24. B. Behin-Aein, A. Sarkar, and S. Datta, “ Modeling circuits with spins and magnets for all-spin logic ,” in 2012 Proceedings of the European Solid-State Device Research Conference ( ESSDERC ) (IEEE, 2012), pp. 36– 40 . 25. B. Behin-Aein, “ Computing multi-magnet based devices and methods for solution of optimization problems ,” U.S. patent 8,698,517 (2014). 26. W. H. Choi, Y. Lv, J. Kim, A. Deshpande, G. Kang, J.-P. Wang, and C. H. Kim, “ A magnetic tunnel junction based true random number generator with conditional perturb and real-time output probability tracking ,” in Proceedings of 2014 IEEE International Electron Devices Meeting ( IEDM ) (IEEE, 2014), pp. 12– 15 . 27. A. Fukushima, T. Seki, K. Yakushiji, H. Kubota, H. Imamura, S. Yuasa, and K. Ando, “ Spin dice: A scalable truly random number generator based on spintronics ,” Appl. Phys. Express 7 , 083001 (2014). https://doi.org/10.7567/APEX.7.083001 28. A. F. Vincent, J. Larroque, N. Locatelli, N. B. Romdhane, O. Bichler, C. Gamrat, W. S. Zhao, J. Klein, S. Galdin-Retailleau, and D. Querlioz, “ Spin-transfer torque magnetic memory as a stochastic memristive synapse for neuromorphic systems ,” IEEE Trans. Biomed. Circuits Syst. 9 , 166– 174 (2015). https://doi.org/10.1109/TBCAS.2015.2414423 29. A. Sengupta, M. Parsa, B. Han, and K. Roy, “ Probabilistic deep spiking neural systems enabled by magnetic tunnel junction ,” IEEE Trans. Electron Devices 63 , 2963– 2970 (2016). https://doi.org/10.1109/TED.2016.2568762 30. Y. Lv and J.-P. Wang, “ A single magnetic-tunnel-junction stochastic computing unit ,” in Proceedings of 2017 IEEE International Electron Devices Meeting ( IEDM ) (IEEE, 2017), pp. 36– 42 . All these approaches work with stable magnets although LBMs could be used to reduce the switching power that is needed.

In this paper, we will focus on unclocked, asynchronous operation using LBM-based hardware accelerators for the BSN [Eq.]. 10. B. Sutton, K. Y. Camsari, B. Behin-Aein, and S. Datta, “ Intrinsic optimization using stochastic nanomagnets ,” Sci. Rep. 7 , 44370 (2017). https://doi.org/10.1038/srep44370 11. R. Faria, K. Y. Camsari, and S. Datta, “ Low-barrier nanomagnets as p-bits for spin logic ,” IEEE Magn. Lett. 8 , 1– 5 (2017). https://doi.org/10.1109/LMAG.2017.2685358 12. K. Y. Camsari, R. Faria, B. M. Sutton, and S. Datta, “ Stochastic p-bits for invertible logic ,” Phys. Rev. X 7 , 031014 (2017). https://doi.org/10.1103/PhysRevX.7.031014 But can an asynchronous circuit provide the sequential updating of the BSN's described by Eq.that is required for Gibbs sampling 31. S. Geman and D. Geman, “ Stochastic relaxation, gibbs distributions, and the bayesian restoration of images ,” IEEE Trans. Pattern Anal. Mach. Intell. 6 , 721– 741 (1984). https://doi.org/10.1109/TPAMI.1984.4767596 and is commonly enforced in software through a for loop ? The answer is “yes” as shown in both SPICE simulations 10. B. Sutton, K. Y. Camsari, B. Behin-Aein, and S. Datta, “ Intrinsic optimization using stochastic nanomagnets ,” Sci. Rep. 7 , 44370 (2017). https://doi.org/10.1038/srep44370 and arduino-based emulations, 32. A. Z. Pervaiz, B. M. Sutton, L. A. Ghantasala, and K. Y. Camsari, “ Weighted p-bits for fpga implementation of probabilistic circuits ,” IEEE Trans. Neural Networks Learn. Syst. (published online). provided that the synaptic function in Eq.has a delay that is less than or comparable to the response time of the BSN, Eq..

It should be noted that unclocked operation is a rarity in the digital world and most applications will probably use a clocked, sequential approach with dedicated sequencers that update connected p-bits sequentially. A fully digital implementation of p-circuits using such dedicated sequencers has been realized in Ref. 32. A. Z. Pervaiz, B. M. Sutton, L. A. Ghantasala, and K. Y. Camsari, “ Weighted p-bits for fpga implementation of probabilistic circuits ,” IEEE Trans. Neural Networks Learn. Syst. (published online). . Synchronous operation can be particularly useful if synaptic delays are large enough to interfere with natural asynchronous operation.

Here, we focus on unclocked operation in order to bring out the role of a p-bit in providing a conceptual bridge between two very active fields of research, namely, stochastic machine learning and quantum computing . On the one hand, p-bits could provide a hardware accelerator for the BSN [Eq.], thereby enabling applications inspired by machine learning (Sec.). On the other hand, p-bits are the classical analogs of q-bits: robust room temperature entities accessible with current technology that could enable at least some of the applications inspired by quantum computing (Sec.). But before we discuss applications, let us briefly discuss possible hardware approaches for implementing p-bits (Sec.).

II. HARDWARE IMPLEMENTATION

A. Three-terminal p-bit

RNGs represent an important component of modern electronics and have been implemented using many different approaches, including Johnson-Nyquist noise of resistors, 33. S. Cheemalavagu, P. Korkmaz, K. V. Palem, B. E. S. Akgul, and L. N. Chakrapani, “ A probabilistic CMOS switch and its realization by exploiting noise ,” in the Proceedings of the IFIP International (2005). phase noise of ring oscillators, 34. M. Bucci, L. Germani, R. Luzzi, A. Trifiletti, and M. Varanonuovo, “ A high-speed oscillator-based truly random number source for cryptographic applications on a smart card IC ,” IEEE Trans. Comput. 52 , 403– 409 (2003). https://doi.org/10.1109/TC.2003.1190581 process variations of: static random-access memory (SRAM) cells, 35. D. E. Holcomb, W. P. Burleson, and K. Fu, “ Power-up SRAM state as an identifying fingerprint and source of true random numbers ,” IEEE Trans. Comput. 58 , 1198– 1210 (2009). https://doi.org/10.1109/TC.2008.212 and other physical mechanisms. However, as noted earlier, we need what appears to be a completely new 3-terminal device whose input I i biases its stochastic output m i as shown in.

A recent paper 13. K. Y. Camsari, S. Salahuddin, and S. Datta, “ Implementing p-bits with embedded MTJ ,” IEEE Electron Device Lett. 38 , 1767– 1770 (2017). https://doi.org/10.1109/LED.2017.2768321 shows that such a 3-terminal tunable RNG can be built simply by combining a 2-terminal fluctuating resistance with a transistor (). This seems to be very attractive at least in the short run since the basic structure [] closely resembles the 1T/MTJ structure commonly used for MRAM applications. The first modification that is required is to replace the stable free layer of the MTJ with an LBM. The second modification is to add an inverter to the drain output that amplifies the fluctuations caused by the MTJ resistance.

FIG. 3. Embedded MRAM p-bit: (a) an NMOS pull-down transistor in series with a stochastic-MTJ whose resistance fluctuates between RP and R AP as shown in (b). (c) Using a 14 nm High Performance (HP)-FinFET model, 43. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “ Predictive technology model ,” (2002), see http://ptm.asu.edu . the input voltage, V in , versus mid-point, V m , and output V out , voltages are simulated in SPICE. Several fixed resistances are shown to convey how V m would vary with modifications to the parallel and anti-parallel resistances.

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An MTJ is a device with two magnetic contacts whose electrical resistance R MTJ takes on one of two values R P and R AP depending on whether the magnets are parallel (P) or antiparallel (AP). MTJs are typically used as memory devices although in recent years, applications of MTJs for logic and novel types of computation have been discussed. 36. J. Wang, H. Meng, and J.-P. Wang, “ Programmable spintronics logic device based on a magnetic tunnel junction element ,” J. Appl. Phys. 97 , 10D509 (2005). https://doi.org/10.1063/1.1857655 37. S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, H. Hasegawa, T. Endoh, H. Ohno, and T. Hanyu, “ Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions ,” Appl. Phys. Express 1 , 091301 (2008). https://doi.org/10.1143/APEX.1.091301 38. H. Ohno, T. Endoh, T. Hanyu, N. Kasai, and S. Ikeda, “ Magnetic tunnel junction for nonvolatile cmos logic ,” in Proceedings of 2010 IEEE International Electron Devices Meeting ( IEDM ) (IEEE, 2010), pp. 9– 4 . 39. A. Lyle, S. Patil, J. Harms, B. Glass, X. Yao, D. Lilja, and J.-P. Wang, “ Magnetic tunnel junction logic architecture for realization of simultaneous computation and communication ,” IEEE Trans. Magn. 47 , 2970– 2973 (2011). https://doi.org/10.1109/TMAG.2011.2158527 40. X. Yao, J. Harms, A. Lyle, F. Ebrahimi, Y. Zhang, and J.-P. Wang, “ Magnetic tunnel junction-based spintronic logic units operated by spin transfer torque ,” IEEE Trans. Nanotechnol. 11 , 120– 126 (2012). https://doi.org/10.1109/TNANO.2011.2158848 41. J. Grollier, D. Querlioz, and M. D. Stiles, “ Spintronic nanodevices for bioinspired computing ,” Proc. IEEE 104 , 2024– 2039 (2016). https://doi.org/10.1109/JPROC.2016.2597152 42. N. Locatelli, V. Cros, and J. Grollier, “ Spin-torque building blocks ,” Nat. Mater. 13 , 11 (2014). https://doi.org/10.1038/nmat3823

Standard MTJ devices go to great lengths to ensure that the magnets they use are stable and can store information for many years. The resistance of bad MTJs, on the other hand, constantly fluctuates between R P and R AP . 3. N. Locatelli, A. Mizrahi, A. Accioly, R. Matsumoto, A. Fukushima, H. Kubota, S. Yuasa, V. Cros, L. G. Pereira, D. Querlioz et al. , “ Noise-enhanced synchronization of stochastic magnetic oscillators ,” Phys. Rev. Appl. 2 , 034009 (2014). https://doi.org/10.1103/PhysRevApplied.2.034009 If we put it in series with a transistor which is a voltage controlled resistance R T ( V in ), then the voltage V m () can be written as Vm=VDD2RT(Vin)−RMTJRT(Vin)+RMTJ.
The magnitude of this fluctuating voltage V m is largest when the transistor resistance R T  ∼  R P or R AP but gets suppressed if R T ≪ R P or if R T ≫ R AP . The input voltage controls R T thereby tuning the stochastic output V m as shown in. It was shown that an additional inverter provides an output that is approximately described by an expression that looks just like the BSN [Eq.] Vout,iVDD/2︷mi≈sgn{tanhVin,iV0︷Ii−r}, (3) but with dimensionless variables like m i and I i replaced by scaled circuit voltages V out and V in .

The scheme inprovides tunability through the series transistor and does not involve the physics of the fluctuating resistor. Ideally, the magnet is unaffected by the change in the transistor resistance though the drain current, in principle, could pin the magnet. In our simulations that are based on Ref. 13. K. Y. Camsari, S. Salahuddin, and S. Datta, “ Implementing p-bits with embedded MTJ ,” IEEE Electron Device Lett. 38 , 1767– 1770 (2017). https://doi.org/10.1109/LED.2017.2768321 , we take the pinning current into account through a spin-polarized current ( I s ) proportional to an effective fixed layer polarization and the drain current (ID), I→s=(P)IDx̂ , where x̂ is the fixed layer direction. This spin-current enters the stochastic Landau-Lifshitz-Gilbert (sLLG) equation that calculates an instantaneous magnetization which in turn controls the MTJ resistance.

We note that any significant pinning around zero input voltage V in ,i has to be minimized through proper design, especially for low barrier perpendicular magnets which are relatively easy to pin. Unintentional pinning 44. C. M. Liyanagedera, A. Sengupta, A. Jaiswal, and K. Roy, “ Stochastic spiking neural networks enabled by magnetic tunnel junctions: From nontelegraphic to telegraphic switching regimes ,” Phys. Rev. Appl. 8 , 064017 (2017). https://doi.org/10.1103/PhysRevApplied.8.064017 should, in general, not be an issue for circular in-plane LBMs due to the strong demagnetizing field. The pinning behavior for the average (steady-state) magnetization can be qualitatively understood by numerical simulations of the sLLG equation. In the case of low-barrier perpendicular magnets, the spin-torque pinning needs to overcome the thermal noise, and therefore, the pinning current is of order IPMA≈2(q/ℏ)αkT , where α is the damping coefficient of the magnet. In the case of circular in-plane magnets, the pinning current is of order IIMA≈2(q/ℏ)αHDMsVol. , which is much larger than I PMA since for typical parameters HDMsVol.≫kT .

Since the state of the magnet is not affected, if the input voltage V in ,i in Eq.is changed at t = 0, the statistics of the output voltage V out ,i will respond within tens of picoseconds (typical transistor switching speeds) 45. D. E. Nikonov and I. A. Young, “ Benchmarking of beyond-cmos exploratory devices for logic integrated circuits ,” IEEE J. Explor. Solid-State Comput. Devices Circuits 1 , 3– 11 (2015). https://doi.org/10.1109/JXCDC.2015.2418033 irrespective of the fluctuation rates of the magnet. However, the magnet fluctuations will determine the correlation time of the random number r in Eq..

Alternatively, one can envision structures where the input controls the statistics of the fluctuating resistor itself, through phenomena such as the spin-Hall effect 12. K. Y. Camsari, R. Faria, B. M. Sutton, and S. Datta, “ Stochastic p-bits for invertible logic ,” Phys. Rev. X 7 , 031014 (2017). https://doi.org/10.1103/PhysRevX.7.031014 or the magneto-electric effect 46. K. Y. Camsari, R. Faria, O. Hassan, B. M. Sutton, and S. Datta, “ Equivalent circuit for magnetoelectric read and write operations ,” Phys. Rev. Appl. 9 , 044020 (2018). https://doi.org/10.1103/PhysRevApplied.9.044020 based on a voltage control of magnetism (see, for example, Refs. 47. A. K. Biswas, H. Ahmad, J. Atulasimha, and S. Bandyopadhyay, “ Experimental demonstration of complete 180° reversal of magnetization in isolated co nanomagnets on a pmn–pt substrate with voltage generated strain ,” Nano Lett. 17 , 3478– 3484 (2017). https://doi.org/10.1021/acs.nanolett.7b00439 and 48. S. Manipatruni, D. E. Nikonov, and I. A. Young, “ Beyond cmos computing with spin and polarization ,” Nat. Phys. 14 , 338 (2018). https://doi.org/10.1038/s41567-018-0101-4 ). In that case, both the speed of response and the correlation time of the random number r will be determined by the specific phenomenon involved.

Non-spintronic implementations: Note that the structure incould use any fluctuating resistor including CMOS-based units in place of the MTJ, showing that the physical realization of a p-bit need not involve spins. 49. M. Jerry, A. Parihar, A. Raychowdhury, and S. Datta, “ A random number generator based on insulator-to-metal electronic phase transitions ,” in Proceedings of 2017 75th Annual Device Research Conference ( DRC ) (IEEE, 2017), pp. 1– 2 . For example, a linear feedback shift register (LFSR) is often used to generate a pseudo-randomly fluctuating bit stream. 50. T. G. Lewis and W. H. Payne, “ Generalized feedback shift register pseudorandom number algorithm ,” J. ACM 20 , 456– 468 (1973). https://doi.org/10.1145/321765.321777 We can apply this fluctuating voltage to the gate of a transistor to obtain a fluctuating resistor which can replace the MTJ in. We note that the main appeal of the structure inlies in its simplicity since a 1T/1MTJ design coupled with two more transistors provides tunable randomness in a compact transistor-like building block. Using completely digital p-circuit implementations 32. A. Z. Pervaiz, B. M. Sutton, L. A. Ghantasala, and K. Y. Camsari, “ Weighted p-bits for fpga implementation of probabilistic circuits ,” IEEE Trans. Neural Networks Learn. Syst. (published online). could offer short term scalability and reliability, but they would consume a much larger area and power per p-bit.

B. Weighted p-bit

The structure ingives us a “neuron” that implements Eq.in hardware. Such neurons have to be used in conjunction with a “synapse” that implements Eq.. Alternatively, we could design a “weighted p-bit” that integrates each element of Eq.with the relevant part of Eq.. For example, we could use floating gate devices along the lines proposed in neuMOS 51. T. Shibata and T. Ohmi, “ A functional MOS transistor featuring gate-level weighted sum and threshold operations ,” IEEE Trans. Electron Devices 39 , 1444– 1455 (1992). https://doi.org/10.1109/16.137325 devices as shown in. From charge conservation, we can write ∑j(Vout,j−Vin,i)Ci,j−Vin,iC0=0, where C 0 is the input capacitance of the transistor. This can be rewritten as Vin,i=∑jCi,jC0+∑jCi,j  Vout,j. By scaling V in and V out [see Eq.] to play the roles of the dimensionless quantities I i and m i , respectively, we can recast Eq.in a form similar to Eq. Vin,iV0︷Ii=∑jVDD2V0Ci,jC0+∑jCi,j︷Wij  Vout,jVDD/2︷mi. (4)

FIG. 4. Example of a weighted p-bit integrating relevant parts of the synapse onto the neurons: leveraging floating-gate devices along the lines proposed in neuMOS 51. T. Shibata and T. Ohmi, “ A functional MOS transistor featuring gate-level weighted sum and threshold operations ,” IEEE Trans. Electron Devices 39 , 1444– 1455 (1992). https://doi.org/10.1109/16.137325 devices; a collection of synapse inputs (from 1 to n) can be summed to produce the bias voltage, V IN,i for a voltage driven p-bit. 52. O. Hassan, K. Y. Camsari, and S. Datta, “ Voltage-driven building block for hardware belief networks ,” e-print arXiv:1801.09026 [cs] (2018).

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The weights W ij can be adjusted by controlling the specific capacitors C ij that are connected. The range of allowed weights and connections is then limited by the routing topology and neuMOS device size. Note that the control of weights through C ij works best if C0≫∑jCij so that W i ,j ≈  C i ,j / C 0 ; however, it is possible to design a weighted p-bit design without this assumption ( C0≫∑Cij ) as discussed in detail in Ref. 52. O. Hassan, K. Y. Camsari, and S. Datta, “ Voltage-driven building block for hardware belief networks ,” e-print arXiv:1801.09026 [cs] (2018). .

Similar control can also be achieved through a network of resistors. The weights are given by the same expression, but with capacitances C ij replaced by conductances G ij . 22. M. Hu, J. P. Strachan, Z. Li, E. M. Grafals, N. Davila, C. Graves, S. Lam, N. Ge, J. J. Yang, and R. S. Williams, “ Dot-product engine for neuromorphic computing: Programming 1t1m crossbar to accelerate matrix-vector multiplication ,” in Proceedings of the 53rd Annual Design Automation Conference ( ACM , 2016), p. 19. However, the input conductance G 0 of FETs is typically very low so that an external conductance has to be added to make G0≫∑jGij .

III. APPLICATIONS OF p-CIRCUITS

As noted earlier, real applications involve p-bits interconnected by a synapse that can be implemented off-chip either in software or with a hardware matrix multiplier, but then it is necessary to transfer data back and forth between Eqs.and. Therefore, a low-level compact hardware implementation of a p-bit along with a local synapse as envisioned incould be a hardware accelerator for many types of applications, some of which will be discussed in this section. In the capacitively weighted p-bit design of, the weights and connectivity of the of the p-bit could be dynamically adjusted based on the encoding of a given problem by leveraging a network of programmable switches 53. G. Lemieux and D. Lewis, Design of Interconnection Networks for Programmable Logic ( Springer US , Boston, MA , 2004). as would be encountered in encountered in field-programmable gate arrays (FPGA). Such a p-bit with local interconnections would look like a compact nanodevice implementation of highly scaled digital spiking neurons of neuromorphic chips such as TrueNorth. 54. P. A. Merolla, J. V. Arthur, R. Alvarez-Icaza, A. S. Cassidy, J. Sawada, F. Akopyan, B. L. Jackson, N. Imam, C. Guo, Y. Nakamura et al. , “ A million spiking-neuron integrated circuit with a scalable communication network and interface ,” Science 345 , 668– 673 (2014). https://doi.org/10.1126/science.1254642 Alternatively, the interconnection function could be performed off-chip using standard CMOS devices such as FPGAs or graphics processing units (GPU), while p-bits are implemented in a standalone chip by modifying embedded MRAM technology. Note, however, an offchip implementation of the interconnection matrix would impose a timing constraint for an asynchronous mode of operation, which requires the weighted summation operation [Eq.] to operate much faster than the p-bit operation [Eq.] for proper convergence. 10. B. Sutton, K. Y. Camsari, B. Behin-Aein, and S. Datta, “ Intrinsic optimization using stochastic nanomagnets ,” Sci. Rep. 7 , 44370 (2017). https://doi.org/10.1038/srep44370 55. A. Z. Pervaiz, L. A. Ghantasala, K. Y. Camsari, and S. Datta, “ Hardware emulation of stochastic p-bits for invertible logic ,” Sci. Rep. 7 , 10994 (2017). https://doi.org/10.1038/s41598-017-11011-8 A full on-chip implementation of a reconfigurable p-bit could function as a low-power, efficient hardware accelerator for applications in Machine Learning and Quantum Computing, but in the near term, a heterogeneous multi-chip synapse/p-bit combination could also prove to be useful.

Now that we have discussed some possible approaches for implementing Eqs.andin hardware, let us present a few illustrative p-bit networks that can implement useful functions and can be built using existing technology. Unless otherwise stated, these results are obtained from full SPICE simulations 56. K. Y. Camsari, S. Ganguly, and S. Datta, “ Modular approach to spintronics ,” Sci. Rep. 5 , 10571 (2015). https://doi.org/10.1038/srep10571 that solve the stochastic Landau-Lifshitz-Gilbert equation coupled with the predictive technology models (PTM)-based transistor models in SPICE 43. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “ Predictive technology model ,” (2002), see http://ptm.asu.edu . to model the embedded MTJ based 3-terminal p-bit described in.

1. Bayesian inference

A natural application of stochastic circuits is in the simulation of networks whose nodes are stochastic in nature (see, for example, Refs. 16. B. Behin-Aein, V. Diep, and S. Datta, “ A building block for hardware belief networks ,” Sci. Rep. 6 , 29893 (2016). https://doi.org/10.1038/srep29893 and 57. L. N. Chakrapani, P. Korkmaz, B. E. Akgul, and K. V. Palem, “ Probabilistic system-on-a-chip architectures ,” ACM Trans. Des. Autom. Electron. Syst. (TODAES) 12 , 29 (2007). https://doi.org/10.1145/1255456.1255466 58. D. Querlioz, O. Bichler, A. F. Vincent, and C. Gamrat, “ Bioinspired programming of memory devices for implementing an inference engine ,” Proc. IEEE 103 , 1398– 1416 (2015). https://doi.org/10.1109/JPROC.2015.2437616 59. Y. Shim, S. Chen, A. Sengupta, and K. Roy, “ Stochastic spin-orbit torque devices as elements for bayesian inference ,” Sci. Rep. 7 , 14101 (2017). https://doi.org/10.1038/s41598-017-14240-z ). An archetypal example is a genetic network, a small version of which is shown in. A well-known concept is that of genetic correlation or relatedness between different members of a family tree. For example, assuming that each of the children C 1 and C 2 gets half their genes from their parents F 1 and M 1 , we can write their correlation as ⟨C1×C2⟩=⟨(0.5F1+0.5M1)×(0.5F1+0.5M1)⟩=14(⟨F1×F1⟩+⟨F1×M1⟩+⟨M1×F1⟩+⟨M1×M1⟩=14(1+0+0+1)=0.5, (5) assuming that F 1 and M 1 are uncorrelated. Hence, the well-known result that siblings have 50% relatedness. Similarly, one can work out the relatedness of more distant relationships like that of an aunt M 1 and her nephew C 3 which turns out to be 25%.

FIG. 5. Genetic circuit: C1 and C2 are siblings with parents F1 and M1, while C3 and C4 are siblings with parents F2 and M2. Two of the parents M1 and F2 are siblings with parents GF1 and GM1. Genetic correlations between different members can be evaluated from the correlations of the nodal voltages in a p-circuit. An XNOR gate finds their product while a long time constant RC circuit provides the time average.

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The point is that we could construct a p-circuit with each of the nodes represented by a hardware p-bit interconnected to reflect the genetic influences. The correlation between two nodes, say C 1 and C 2 , is given by ⟨C1×C2⟩=∫0TdtT C1(t)C2(t). (6) If C 1 (t) and C 2 (t) are binary variables with allowed values of 1 and 0, then they can be multiplied in hardware with an AND gate. If the allowed values are bipolar, −1 and +1, then the multiplication can be implemented with an XNOR gate. In either case, the average over time can be performed with a long time constant RC-circuit. A few typical results from SPICE simulations are shown in. The numerical results inare in good agreement with Bayes theorem even though the circuit operates asynchronously without any sequencers. This is interesting since software simulations of Eqs.andwith directed weights usually require the nodes to be updated from parent to child. Whether this behavior generalizes to larger directed networks is left for future work.

We use this genetic circuit as a simple illustration of the concept of nodal correlations which appear in many other contexts in everyday life. Medical diagnosis, 60. W. Tylman, T. Waszyrowski, A. Napieralski, M. Kamiński, T. Trafidło, Z. Kulesza, R. Kotas, P. Marciniak, R. Tomala, and M. Wenerski, “ Real-time prediction of acute cardiovascular events using hardware-implemented bayesian networks ,” Comput. Biol. Med. 69 , 245– 253 (2016). https://doi.org/10.1016/j.compbiomed.2015.08.015 for example, involve symptoms such as, say high temperature, which can have multiple origins or parents, and one can construct Bayesian networks to determine different causal relationships of interest.

2. Accelerating learning algorithms

Networks of p-bits could be useful in implementing inference networks, where the network weights are trained offline by a learning algorithm in software and the hardware is used to repeatedly perform inference tasks efficiently. 61. A. Ardakani, F. Leduc-Primeau, N. Onizawa, T. Hanyu, and W. J. Gross, “ Vlsi implementation of deep neural network using integral stochastic computing ,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 , 2688– 2699 (2017). https://doi.org/10.1109/TVLSI.2017.2654298 62. R. Zand, K. Y. Camsari, S. D. Pyle, I. Ahmed, C. H. Kim, and R. F. DeMara, “ Low-energy deep belief networks using intrinsic sigmoidal spintronic-based probabilistic neurons ,” in Proceedings of the 2018 on Great Lakes Symposium on VLSI (ACM, 2018), pp. 15– 20 .

Another common example where correlations play an important role is in the learning algorithms used to train modern neural networks like the restricted Boltzmann machine (RBM) () 63. R. Salakhutdinov, A. Mnih, and G. Hinton, “ Restricted Boltzmann machines for collaborative filtering ,” in Proceedings of the 24th International Conference on Machine Learning (ACM, 2007), pp. 791– 798 . having a visible layer and a hidden layer, with connecting weights W ij linking nodes of one layer to those in the other, but not within a layer. A widely used algorithm based on “contrastive divergence” 64. G. E. Hinton, “ Training products of experts by minimizing contrastive divergence ,” Neural Comput. 14 , 1771– 1800 (2002). https://doi.org/10.1162/089976602760128018 adjusts each weight W ij according to ΔWij∼⟨vihj⟩t=0−⟨vihj⟩t→∞, which requires the repeated evaluation of the correlations ⟨vihj⟩ . Computing such correlations exactly becomes intractable due to their exponential complexity in the number of neurons; therefore, contrastive divergence is often limited by a fixed number of steps (CDn) to limit the number of repeated evaluation of these correlations. This process could be accelerated through an efficient physical representation of the neuron and the synapse. 65. M. N. Bojnordi and E. Ipek, “ Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning ,” in Proceedings of 2016 IEEE International Symposium on High Performance Computer Architecture ( HPCA ) (IEEE, 2016), pp. 1– 13 . 66. R. Faria, J. Kaiser, O. Hassan, K. Y. Camsari, and S. Datta, “ Accelerating machine learning using stochastic embedded mtj ” (unpublished).

FIG. 6. Restricted Boltzmann Machine (RBM): RBMs are a special class of stochastic neural networks that restrict connections within a hidden and a visible layer. Standard learning algorithms require repeated evaluations of correlations of the form ⟨vihj⟩ .

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B. Applications: Quantum inspired

The functionality of neural networks is determined by the weight matrix W ij which determines the connectivity among the neurons. They can be classified broadly by the relation between W ij and W ji . In traditional feedforward networks, information flow is directed with neuron “i” influencing neuron “j” through a non-zero weight W ij but with no feedback from neuron “j,” such that W ji = 0. At the other end of the spectrum is a network with all connections being reciprocal W ij = W ji . In between these two extremes is the class of networks for which the weights between two nodes are asymmetric, but non-zero.

The class of networks with symmetric connections is particularly interesting since they are closely parallel to classical statistical physics where the natural connections between interacting particles are symmetric and the equilibrium probabilities are given by the celebrated Boltzmann law expressing the probability of a particular configuration α in terms of an energy E α associated with that configuration Pα=1Z  exp(−Eα), (7) Eα=−{m}αT  [W]  {m}α, (8) where T denotes transpose and constant Z is chosen to ensure that all Pα′s add up to one. This energy principle is only available for reciprocal networks 67. D. J. Amit and D. J. Amit, Modeling Brain Function: The World of Attractor Neural Networks ( Cambridge University Press , 1992). and can be very useful in determining the appropriate weights W ij for a particular problem.

This class of networks connects naturally to the world of quantum computing which is governed by Hermitian Hamiltonians and is also the subject of the emerging field of Ising computing . 10. B. Sutton, K. Y. Camsari, B. Behin-Aein, and S. Datta, “ Intrinsic optimization using stochastic nanomagnets ,” Sci. Rep. 7 , 44370 (2017). https://doi.org/10.1038/srep44370 16. B. Behin-Aein, V. Diep, and S. Datta, “ A building block for hardware belief networks ,” Sci. Rep. 6 , 29893 (2016). https://doi.org/10.1038/srep29893 68. M. Yamaoka, C. Yoshimura, M. Hayashi, T. Okuyama, H. Aoki, and H. Mizuno, “ A 20k-spin ising chip to solve combinatorial optimization problems with cmos annealing ,” IEEE J. Solid-State Circuits 51 , 303– 309 (2016). https://doi.org/10.1109/JSSC.2015.2498601 69. P. L. McMahon, A. Marandi, Y. Haribara, R. Hamerly, C. Langrock, S. Tamate, T. Inagaki, H. Takesue, S. Utsunomiya, K. Aihara et al. , “ A fully programmable 100-spin coherent ising machine with all-to-all connections ,” Science 354 , 614– 617 (2016). https://doi.org/10.1126/science.aah5178 70. Y. Shim, A. Jaiswal, and K. Roy, “ Ising computation based combinatorial optimization using spin-hall effect (she) induced stochastic magnetization reversal ,” J. Appl. Phys. 121 , 193902 (2017). https://doi.org/10.1063/1.4983636 71. T. Wang and J. Roychowdhury, “ Oscillator-based ising machine ,” preprint arXiv:1709.08102 (2017). 72. T. Van Vaerenbergh, R. Bose, D. Kielpinski, G. J. Mendoza, J. S. Pelc, N. A. Tezak, C. Santori, and R. G. Beausoleil, “ How coherent ising machines push circuit design in silicon photonics to its limits (conference presentation) ,” Proc. SPIE 10537 , 105370D (2018). https://doi.org/10.1117/12.2288586

1. Invertible Boolean logic

Suppose that, for example, we wish to design a Boolean gate which will provide three outputs reflecting the AND, OR, and XNOR functions of the two inputs A and B. The truth table is shown in. Note that although we are using the binary notations 1 and 0, they actually stand for p-bit values of +1 and −1, respectively.

FIG. 7. Invertible Boolean logic: a multi-function Boolean gate with 6 p-bits is shown. Inputs A and B produce the output for a 2-input XNOR, AND, and OR gate, respectively. The handle bit, “h,” is used to remove the complementary low-energy states that do not belong to the truth table shown. In the unclamped mode, the system shows the states corresponding to the lines of the truth table with high probability. A and B can be clamped to produce the correct output for the XNOR, AND, and OR in the direct mode. In the inverse mode, any one of the outputs (XNOR is shown as an example) can be clamped to a given value, and the inputs fluctuate among possible input combinations corresponding to this output.

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Since there are five p-bits, two representing the inputs and three representing the outputs, the system has 2 5 = 32 possible states, which can be indexed by their corresponding decimal values. Each of these configurations has an associated energy, E n , n  =   0, 1, …, 31. What we need is a weight matrix W ij such that the desired configurations 4, 9, 17, and 31 (in decimal notation) specified by the truth table have a low energy E α [Eq.] compared to the rest so that they are occupied with higher probability. This can be done either by using the principles of linear algebra 12. K. Y. Camsari, R. Faria, B. M. Sutton, and S. Datta, “ Stochastic p-bits for invertible logic ,” Phys. Rev. X 7 , 031014 (2017). https://doi.org/10.1103/PhysRevX.7.031014 or by using machine learning algorithms 73. G. E. Hinton, “ A practical guide to training restricted Boltzmann machines ,” in Neural networks: Tricks of the trade (Springer, 1985); available at https://link.springer.com/chapter/10.1007/978-3-642-35289-8_32 . to obtain the weight matrix shown in. Note that an additional p-bit labeled “h” has been introduced which is clamped to a value of +1 by applying a large bias.

On the right of, a histogram shows the frequency of all the possible (32) configurations obtained from a simulation of Eqs.andusing this weight matrix. Similar results are obtained from a SPICE simulation of a p-circuit of weighted p-bits. Note the peaks at the desired truth table values, with smaller peaks at some of the undesired values. The peaks closely follow the Boltzmann law, such that PdesiredPundesired=exp(Eundesired−Edesired). Undesired peaks can be suppressed if we make the W-matrix larger, say by an overall multiplicative factor of 2. If all energies are increased by a factor of 2, the ratio of probabilities would be squared: a ratio of 10 would become a ratio of 100.

It is also possible to operate the gate in a traditional feed-forward manner where inputs are specified and an output is obtained. This mode is shown in the middle panel on the right where the inputs A and B are clamped to 1 and 0, respectively. Only one of the four truth table peaks can be seen, namely, the line corresponding to A = 1 and B = 0, which is labeled 17.

What is more interesting is that the gates can be run in inverse mode as shown in the lower right panel. The XNOR output is clamped to 0 corresponding to specific lines of the truth table corresponding to 9 and 17. The inputs now fluctuate between the two possibilities, indicating that we can use these gates to provide us with all possible inputs consistent with a specified output, a mode of operation not possible with standard Boolean gates.

This invertible mode is particularly interesting because there are many cases where the direct problem is relatively easy compared to the inverse problem. For example, we can find a suitable weight matrix to implement an adder that provides the sum S of numbers A, B, and C. But the same network also solves the inverse problem where a sum S is provided and it finds combinations of k numbers that add up to S. 32. A. Z. Pervaiz, B. M. Sutton, L. A. Ghantasala, and K. Y. Camsari, “ Weighted p-bits for fpga implementation of probabilistic circuits ,” IEEE Trans. Neural Networks Learn. Syst. (published online). 52. O. Hassan, K. Y. Camsari, and S. Datta, “ Voltage-driven building block for hardware belief networks ,” e-print arXiv:1801.09026 [cs] (2018). This inverse k-sum or subset sum problem is known to be NP-complete 74. K. G. Murty and S. N. Kabadi, “ Some np-complete problems in quadratic and nonlinear programming ,” Math. Program. 39 , 117– 129 (1987). https://doi.org/10.1007/BF02592948 and is clearly much more difficult than direct addition. Similarly, we can design a weight matrix such that the network multiplies any two numbers. In the inverse mode, the same network can factorize a given number, which is a hard problem. 75. P. W. Shor, “ Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer ,” SIAM Rev. 41 , 303– 332 (1999). https://doi.org/10.1137/S0036144598347011 This ability to factorize has been shown with relatively small numbers. 12. K. Y. Camsari, R. Faria, B. M. Sutton, and S. Datta, “ Stochastic p-bits for invertible logic ,” Phys. Rev. X 7 , 031014 (2017). https://doi.org/10.1103/PhysRevX.7.031014 32. A. Z. Pervaiz, B. M. Sutton, L. A. Ghantasala, and K. Y. Camsari, “ Weighted p-bits for fpga implementation of probabilistic circuits ,” IEEE Trans. Neural Networks Learn. Syst. (published online). How well p-circuits will scale to larger factorization problems remains to be explored.

It is worth mentioning that this method of solving integer factorization and the subset sum problem is similar to the deterministic “memcomputing” framework where a “self-organizing logic circuit” is set up to solve the direct problem and operated in reverse to solve the inverse problem (see, for example, Refs. 76. F. L. Traversa and M. Di Ventra, “ Polynomial-time solution of prime factorization and np-complete problems with digital memcomputing machines ,” Chaos 27 , 023107 (2017). https://doi.org/10.1063/1.4975761 and 77. M. Di Ventra and F. L. Traversa, “ Perspective: Memcomputing: Leveraging memory and physics to compute efficiently ,” J. Appl. Phys. 123 , 180901 (2018). https://doi.org/10.1063/1.5026506 ).

2. Optimization by classical annealing

It has been shown that many optimization problems can be mapped onto a network of classical spins with an appropriate weight matrix, such that the optimal solution corresponds to the configuration with the lowest energy. 78. A. Lucas, “ Ising formulations of many np problems ,” Front. Phys. 2 , 5 (2014). https://doi.org/10.3389/fphy.2014.00005 Indeed, even the problem of integer factorization discussed above in terms of inverse multiplication can alternatively be addressed in this framework by casting it as an optimization problem. 79. X. Peng, Z. Liao, N. Xu, G. Qin, X. Zhou, D. Suter, and J. Du, “ Quantum adiabatic algorithm for factorization and its experimental implementation ,” Phys. Rev. Lett. 101 , 220405 (2008). https://doi.org/10.1103/PhysRevLett.101.220405 80. P. Henelius and S. Girvin, “ A statistical mechanics approach to the factorization problem ,” e-print arXiv:1102.1296 [cond-mat]. 81. S. Jiang, K. A. Britt, T. S. Humble, and S. Kais, “ Quantum annealing for prime factorization ,” Sci. Rep. 8 , 1– 9 (2018). https://doi.org/10.1038/s41598-018-36058-z

A well-known example of an optimization problem is the classic N-city traveling salesman problem (TSP). It involves finding the shortest route by which a salesman can visit all cities once starting from a particular one. This problem has been mapped to a network of ( N – 1) 2 spins where each spin has two indices, the first denoting the order in which a city is visited and the second denoting the city.

shows a 5-city TSP mapped to a 16 p-bit network and translated into a p-circuit that is simulated using SPICE. The overall W-matrix is slowly increased and with increasing interaction the network gradually settles from a random state into a low energy state. This process is often called simulated annealing 82. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, “ Optimization by simulated annealing ,” Science 220 , 671– 680 (1983). https://doi.org/10.1126/science.220.4598.671 based on the similarity with the freezing of a liquid into a solid with a lowering of temperature in the physical world, which reduces the random thermal energy relative to a fixed interaction.

FIG. 8. Combinatorial optimization: a 5-city Traveling Salesman Problem (TSP) implemented using a network of 16 p-bits (fixing city 0), each having two indices, the first denoting the order in which a city is visited and the second denoting the city. The interaction parameter I0 scales all weights and acts as an inverse temperature and is slowly increased via a simple annealing schedule I0(t+teq)=(1/0.99)I0(t) to guide the system into the lowest energy state, providing the shortest traveling distance (Map imagery data: Google, TerraMetrics).

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Note that at high values of interaction, the p-bits settle to the correct solution with four p-bits highlighted corresponding to (1,1), (2,3), (3,2), and (4,4), showing that the cities should be visited in the order 1–3–2–4. Unfortunately, things may not work quite so smoothly as we scale up to problems with larger numbers of p-bits. The system tends to get stuck in metastable states just as in the physical world solids develop defects that keep them from reaching the lowest energy state.

3. Optimization by quantum annealing

An approach that has been explored is the process of quantum annealing using a network of quantum spins implemented with superconducting q-bits. 83. J. Mooij, T. Orlando, L. Levitov, L. Tian, C. H. Van der Wal, and S. Lloyd, “ Josephson persistent-current qubit ,” Science 285 , 1036– 1039 (1999). https://doi.org/10.1126/science.285.5430.1036 84. M. W. Johnson, M. H. Amin, S. Gildert, T. Lanting, F. Hamze, N. Dickson, R. Harris, A. J. Berkley, J. Johansson, P. Bunyk et al. , “ Quantum annealing with manufactured spins ,” Nature 473 , 194 (2011). https://doi.org/10.1038/nature10012 However, it is known that for certain classes of quantum problems classified by “stoquastic” Hamiltonians, 85. T. Albash and D. A. Lidar, “ Adiabatic quantum computation ,” Rev. Mod. Phys. 90 , 015002 (2018). https://doi.org/10.1103/RevModPhys.90.015002 a network of q-bits can be approximated with a larger network of p-bits operating in hardware (). 86. K. Y. Camsari, S. Chowdhury, and S. Datta, “ Scaled quantum circuits emulated with room temperature p-bits ,” preprint arXiv:1810.07144 (2018). We have made use of this equivalence to design p-circuits whose SPICE simulations show correlations and averages comparable to those obtained with quantum annealers. 86. K. Y. Camsari, S. Chowdhury, and S. Datta, “ Scaled quantum circuits emulated with room temperature p-bits ,” preprint arXiv:1810.07144 (2018).

FIG. 9. Mapping a q-bit network into a p-bit network: a special class of quantum many body Hamiltonians that are “stoquastic” can be solved by mapping them to a classical network of p-bits that consist of a finite number of replicas of the original system that are interacting in the “vertical” direction. This approach implemented in software is also known as the Path Integral Monte Carlo method. A hardware implementation would constitute a p-computer that is capable of performing quantum annealing. 86. K. Y. Camsari, S. Chowdhury, and S. Datta, “ Scaled quantum circuits emulated with room temperature p-bits ,” preprint arXiv:1810.07144 (2018).

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IV. CONCLUSIONS

In summary, we have introduced the concept of a probabilistic or p-bit, intermediate between the standard bits of digital electronics and the emerging q-bits of quantum computing. Low barrier magnets or LBMs provide a natural physical representation for p-bits and can be built either from perpendicular magnets (PMA) designed to be close to the in-plane transition or from circular in-plane magnets (IMA). Magnetic tunnel junctions (MTJ) built using LBMs as free layers can be combined with standard NMOS transistors to provide three-terminal building blocks for large scale probabilistic circuits that can be designed to perform useful functions. Interestingly, this three-terminal unit looks just like the 1T/MTJ device used in embedded MRAM technology, with only one difference: the use of an LBM for the MTJ free layer. We hope that this concept will help open up new application spaces for this emerging technology. However, a p-bit need not involve an MTJ; any fluctuating resistor could be combined with a transistor to implement it. It may be interesting to look for resistors that can fluctuate faster based on entities like natural and synthetic antiferromagnets, 87. K. Y. Camsari, A. Z. Pervaiz, R. Faria, E. E. Marinero, and S. Datta, “ Ultrafast spin-transfer-torque switching of synthetic ferrimagnets ,” IEEE Magn. Lett. 7 , 1– 5 (2016). https://doi.org/10.1109/LMAG.2016.2610942 88. U. Atxitia, T. Birk, S. Selzer, and U. Nowak, “ Superparamagnetic limit of antiferromagnetic nanoparticles ,” preprint arXiv:1808.07665 (2018). for example.

The p-bit also provides a conceptual bridge between two active but disjoint fields of research, namely, stochastic machine learning and quantum computing. This viewpoint suggests two broad classes of applications for p-bit networks. First, there are the applications that are based on the similarity of a p-bit to the binary stochastic neuron (BSN), a well-known concept in machine learning. Three-terminal p-bits could provide an efficient hardware accelerator for the BSN. Second, there are the applications that are based on the p-bit being like a poor man's q-bit. We are encouraged by the initial demonstrations based on full SPICE simulations that several optimization problems, including quantum annealing are amenable to p-bit implementations which can be scaled up at room temperature using existing technology.

ACKNOWLEDGMENTS

S.D. is grateful to Dr. Behtash Behin-Aein for many stimulating discussions leading up to Ref. 16. B. Behin-Aein, V. Diep, and S. Datta, “ A building block for hardware belief networks ,” Sci. Rep. 6 , 29893 (2016). https://doi.org/10.1038/srep29893 .

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