Chip Industry’s Technical Paper Roundup: May 23
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Chip Industry’s Technical Paper Roundup: May 23
Edge with RISC-V and HW accelerators; RL-guided routing; memory mapping using DL; cross-shape reconfigurable FET; memory disaggregation; EV charging security issues; PCM for analog in-memory computing; non-traditional design of dynamic logic using FDSOI; semiconductor optical amplifiers in data centers.
New technical papers recently added to Semiconductor Engineering’s library:
Technical Paper | Research Organizations |
---|---|
EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators | Columbia University |
Reinforcement Learning Guided Detailed Routing for Custom Circuits | UT Austin, Princeton University, and NVIDIA |
Optimizing Memory Mapping Using Deep Reinforcement Learning | Google DeepMind and Google |
Cross-Shape Reconfigurable Field Effect Transistor for Flexible Signal Routing | NaMLab gGmbH, École Centrale de Lyon, and TU Dresden |
Memory Disaggregation: Advances and Open Challenges | University of Michigan |
ChargeX: Exploring State Switching Attack on Electric Vehicle Charging Systems | Michigan State University, Washington University in St. Louis, and Texas A&M University |
Optimization of Projected Phase Change Memory for Analog In-Memory Computing Inference | IBM Research |
Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing | University of Stuttgart, UC Berkeley, Indian Institute of Technology Kanpur, and TU Munich |
Integrated SOAs enable energy-efficient intra-data center coherent links | UC Santa Barbara |
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Linda Christensen
Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
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