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Sure, SPR+HBM probably uses a different substrate. But the package size, core/tile counts doesn't change. There's enough space on the package from what I can tell.

They’re going to have to get creative with the lid seal on the right side if you drop HBMs out there, as it leaves very little room

This is an early sample I believe. In final production silicon, the tiles could be more centered.

You’ve got 77.6 total, 40 for the tiles, 20 for HBM, some gaps, leaving 17+ for discretes, seal band etc. There’s a solution in there, but starting with a centered array is likely key.

Probably. I don't doubt that the package/socket and core/tile counts will be the same for both HBM and non-HBM SKUs.

Interesting picture from an Intel 2021 ECTC presentation on EMIB optimization -- the 10 small EMIB sites match the layout for Sapphire Rapids, and there are 4 larger sites that could represent 4 HBM's -- interesting that they're all on one side of the carrier

Having six emib on one dimension and four emib in the other doesn't make much sense, does it? Surely you need some level of parity here. If Intel have been smart, all the tiles are identical but rotated.

I was expecting symmetry, the first rip-up showed otherwise

And Ian, shouldn’t you be focused on the Euro match?

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I eat wafers | 10 Yr Senior CPU Editor, http://AnandTech.com | TechTechPotato